Accucell Examples

• 001_cell : AccuCell Configuration Files
• 002_cell : Automatic Configuration From a Liberty File
• 003_cell : Controlling SPICE simulations
• 004_cell : Re-Use, Multi-Threading and SUN Grid Engine(SGE)
• 005_cell : Optimal Slopes and Loads
• 006_cell : NLPM Power and Leakage Characterization
• 007_cell : CCS Timing Characterization
• 008_cell : Setup/Hold Characterization
• 009_cell : Minimum Pulse Width Characterization
• 010_cell : Integrated Clock Gating Cell Characterization
• 011_cell : Verilog Simulation Models
• 012_cell : AccuCell QA and Audit Options and Methods
• 013_cell : ONE_HOT Reduced Vector Sets for Wide MUX Cells
• 014_cell : Cells with Unbuffered Passgate Inputs
• 015_cell : Tristate Cells
• 016_cell : Bi-directional I/O Pads
• 017_cell : Level shifters
• 018_cell : Characterization with Multiple Clocks
• 019_cell : Use of ONE_HOT with Differential Input Cells
• 020_cell : .tbl Table File Basics
• 021_cell : Setup/Hold Induced CLK-to-Q Degradation
• 022_cell : Recovery/Removal Characterization
• 023_cell : Scan Enable Flip-Flop Characterization
• 024_cell : Spectre Netlist and Model Support
• 025_cell : RS Latch Characterization
• 026_cell : ACTIVE DRIVER Characterization
• 027_cell : 3D Timing for Sequential Cells with Dependent Outputs