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疑难解答/FAQ

EDA SMARTSPICE

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Q1
Q2
Q3
Q4

Q1
当前我们需要模拟很多电路(15个任务),由于授权个数有限,不能把命令行一个一个都打上。怎样使用Smartspice顺次进行多次仿真?

A1

我们可以使用"Spiceserver"工具(在Linux/Unix 操作系统下)来进行任务队列仿真,它可以让Smartspice 顺次进行多个批处理的仿真任务。 在Smartspice 使用手册第一册,第一章,第七节,有对"Spiceserver"的简要介绍。下面我们通过一个例子,对这个工具的设置和使用提供一些补充信息。
   
 
1. 创建临时文件夹
首先,我们要为"Spiceserver”"创建临时文件夹。我们可以指定以下路径: "/SPICESERVER_TMP", "/TMP" 或者 "/TEMP". 建议把临时文件夹设在本地路径下,因为在远程电脑上生成/读写临时文件会在一定程度上减缓仿真的速度。

2. 设置环境变量
如果我们使用的是C-shell, 请在用户的".cshrc" 文件中 (下载此文件) 加入下面几行,指出临时文件夹的位置。除此以外,我们也可以在此设置SPICESERVER_TIMEOUT变量。

setenv SPICESERVER_TMP /SPICESERVER_TMP
setenv TMP /TMP
setenv TEMP /TEMP
setenv SPICESERVER_TIMEOUT 300

如果我们使用bash, 则改用以下语法:

export SPICESERVER_TMP = /SPICESERVER_TMP
export TMP= /TMP
export TEMP=/TEMP
export SPICESERVER_TIMEOUT=300

3. 创建一个脚本文件
我们可以把需要仿真的任务集中起来,按照想要的次序排列。把这些记录在一个脚本文件里,运行该脚本文件的时候所有的任务就会顺次运行。

举个例子,如果我们打算依次运行以下Smartspice输入文件: "ex1.in" 至 "ex8.in" (位于<Silvaco_安装路径>/examples/Smartspice/<版本号>.)我们可以创建脚本文件"queue_simulation" (下载此文件), 其内容如下:

spiceserver -start
spiceserver -f ex1.in -o ex1.test.out -r ex1.test.raw
spiceserver -f ex2.in -o ex2.test.out -r ex2.test.raw
spiceserver -f ex3.in -o ex3.test.out -r ex3.test.raw
spiceserver -f ex4.in -o ex4.test.out -r ex4.test.raw
spiceserver -f ex5.in -o ex5.test.out -r ex5.test.raw
spiceserver -f ex6.in -o ex6.test.out -r ex6.test.raw
spiceserver -f ex7.in -o ex7.test.out -r ex7.test.raw
spiceserver -f ex8.in -o ex8.test.out -r ex8.test.raw
spiceserver -stop

4. 运行此脚本文件.
在工作站终端, "cd" 去脚本文件所在路径,运行:
./queue_simulation

此时如果授权数目足够,"Spiceserver" 就会顺次运行各个仿真, 并在最后一个仿真结束后释放授权。

 
下面是终端里输出:


SPARC-Solaris10# ./queue_simulation
Running 32 bits version
Running in 64 bit mode.
Running 32 bits version
Running 32 bits version
Running 32 bits version
Running 32 bits version
Running 32 bits version
Running 32 bits version
Running 32 bits version
Running 32 bits version
Running 32 bits version
default on SPARC-Solaris10 [0x40000001] v3.6.8.R Status: Available (Idle)
Stopped
SPARC-Solaris10# Smartview&

在指定的路径下, 8个仿真任务依次结束了,产生相应的raw文件。用Smartview 可以查看波形(下图选取其中两个)。

   
 
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Q2
How do I make my long simulation more memory efficient?

A2

When we run a long simulation time analysis the evaluated time points are normally all held in memory until the end time is reached. All the data is then written out to the output rawfile. This means a large amount of system memory can be used up and also has to be tracked.

If in the input deck the line “.OPTIONS RAWPTS=300 POST” is included then as soon as the maximum number of points is reached given by “RAWPTS=300” then all the vector data is saved to the raw data output file and the memory is free to be re-used. In this way the output rawfile is incrementally increased in size every time this limit is reached. The memory required by the simulation run is therefore reduced, and with less memory to manage, the simulation is run faster.

This is particularly useful on the PC platform where some of the memory is required for the operating system and RAM size is less than 1Gig.
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Q3
I have set the RAWPTS option in my input deck when I ran transient; however, if my simulation is terminated unexpected, how can recover previous simulation result and resume the remaining part?

A3

SMARTSPICE is capable of recovering from an unexpected program termination during a transient analysis simulation. This functionality is performed through so called checkpoint files and is disabled by default. It can be activated through the environment variable or command line option +checkpoint.

For example, for an input deck that contains either of following statement/option:

.TRAN 0.1NS 1000u ckptperiod=20
or
.option CKPTCLOCK=20


Where "20" refers to the time interval (in unit of second) for Smartspice to save transient data into an “.sav” file.

If it is run with “smartspice +checkpoint” command, the .sav file will be saved in every 20 seconds.

If the simulation was terminated, the transient analysis can be restored by “smartspice +checkpoint +recover” command, loading the “.sav” file that we just saved previously.

If we are simulating a large circuit for a very long transient time, beside RAWPTS and above checkpoint-restore feature, we can add “.OPTIONS SAFEMODE” to warn users if the simulation run consumers too much resources. Another way is instead of the “.SAVE ALL” we can record certain vectors of interest from part of whole circuit.
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Q4
我对Smartspice 中的Verilog-A 功能比较感兴趣, 所以就用随安装包带来的例子试验。 可是无法运行, 报错为:

Warning: (VERILOGA): Execution mode set to 'vcc'.

The following command exited with error code 1 :
cl /nologo /GR /GX /O2 /Op /Ob2 /c mosfet-module.c /o mosfet-module.obj
The following command exited with error code 1 :
link /nologo mosfet-module.obj /DLL /out:mosfet-module.dll C:\sedatools\lib\smartspice\3.8.7.C\x86-nt\\VLGA\..\smartspice.lib
Error: (VERILOGA): Compilation of bsim4.va ... failed
Error: (VERILOGA): Failed finding model 'mosfet'

等等。请问是什么原因? 怎么解? 我又尝试运行了一下Harmony 里面的例子, 可是也出现了错误。 感觉是Smartspice 和 Harmony 在编译Verilog-A的时候出错。

A4

这是因为你的电脑设置了使用微软的C/C++ 编译器, 但是由于某种原因 (比如没有安装该编译器)此编译器失败。 我们可以设置环境变量"SMARTSPICE_VERILOGA_MODE" 从缺省的"vcc" 变为 “sci”。 这个变量对Smartspice 和 Harmony 都有效。 请参照下图:
   
 
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