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全定制 IC CAD
| EDA产品的最新信息 |
| 2-018 |  EN
| Layout Verification in Batch Mode |
| 2-017 | EN
| Efficient Bus Wiring in Expert |
| 2-016 | EN
| Tips to Make PCells Using Javascript |
| 2-015 | EN
| New Features Facilitate DRC Clean Layout and Parasitic Effect Debugging |
| 2-014 | EN
| How to Modify MOSFET PCells for Expert’s Device Link |
| 2-013 | EN
| Enabling Netlist Driven Layout with Standard Cells |
| 2-012 | EN
| New Enhanced Possibilities of Netlist Comparison in Guardian LVS |
| 2-011 | EN
| Using DRC Error Database to Analyze LVL Run Results |
| 2-010 | EN
| Parasitic Back Annotation for Post Layout Simulation |
| 2-009 | EN
| Creating LISA Scripts to Automate Layout Operations in Expert |
| 2-008 | EN
| Customizing EXPERT with New Functions Using LISA |
| 2-007 | EN
| Preserving Parametrized Cells When Translating Competitors’ Layout Database into Expert |
| 2-006 | EN
| Central HIPEX Database and Improved HIPEX-C and HIPEX-R Technology Files |
| 2-005 | EN
| Selective RC-extraction Methods in Guardian LPE for Post-layout Circuit Simulations |
| 2-004 | EN
| A Suggested Approach for Layout Versus Schematic (LVS) Comparison Using Guardian LVS |
| 2-003 | EN
| Logic Gate recognition in Guardian LVS |
| 2-002 | EN
| Well Proximity and STI Stress Effect Parameters Extraction in Guardian LPE |
| 2-001 | EN
| Multi-Core Guardian DRC Benchmark Results |
