Daewoong Kang, Hyungcheol Shin,
"Improving the cell characteristics using arch-active profile in NAND flash memory having 60 nm design-rule",
Solid-State Electronics, Vol. 54, Issue 11, November 2010, pp. 1263-1268.
Seongjae Cho, Jung-Dal Choi, Byung-Gook Park, Il Hwan Cho,
"Effects of channel doping concentration and fin dimension variation on self-boosting of channel potential in NAND-type SONOS flash memory array based on bulk-FinFETs",
Current Applied Physics, Vol. 10, Issue 4, July 2010, pp. 1096-1102.
M.A. Garcia-Ramirez, Yoshishige Tsuchiya, Hiroshi Mizuta,
"Hybrid circuit analysis of a suspended gate silicon nanodot memory (SGSNM) cell",
Microelectronic Engineering, Vol. 87, Issues 5-8, May-August 2010, pp. 1284-1286.
Kyoung-Rok Han, Min-Kyu Jeong, Ilwhan Cho, Jong-Ho Lee,
"5-bit/cell Characteristics using mixed program/erase mechanism in recessed channel non-volatile memory cells",
Current Applied Physics, Vol. 10, Issue 1, Supplement 1, January 2010, pp. e2-e4.
A. Abdul Aziz, N. Soin,
"Dependency of threshold voltage on floating gate and inter-polysilicon dielectric thickness for nonvolatile memory devices",
2010 IEEE International Conference on Semiconductor Electronics (ICSE), 2010, pp. 83 - 87.
Yoon Kim, Seongjae Cho, Gil Sung Lee, Il Han Park, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park,
"3-dimensional terraced NAND (3D TNAND) flash memory-stacked version of folded NAND array",
IEICE Transactions on Electronics, Vol. E92-C, No. 5, May 2009, pp. 653-658
Shin-ichi O’uchi, Kazuhiko Endo, Meishoku Masahara, Kunihiro Sakamoto, Yongxun Liu, Takashi Matsukawa, Toshihiro Sekigawa, Hanpei Koike, Eiichi Suzuki,
"Flex-pass-gate SRAM for static noise margin enhancement using FinFET-based technology",
Solid-State Electronics, Vol. 52, Issue 11, November 2008, pp. 1694-1702
Jang-Gn Yun, Yoon Kim, Il Han Park, Jung Hoon Lee, Sangwoo Kang, Dong-Hua Lee, Seongjae Cho, Doo-Hyun Kim, Gil Sung Lee, Won-Bo Sim, Younghwan Son, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park,
"Fabrication and characterization of fin SONOS flash memory with separated double-gate structure",
Solid-State Electronics, Vol. 52, Issue 10, October 2008, pp. 1498-1504
Mohammad Gh. Mohammad, Kewal K. Saluja
"Analysis and test procedures for NOR
flash memory defects,"
Microelectronics Reliability, Vol. 48, Issue 5, May 2008,
pp. 698-709.
Hiroaki Yamazaki, Hiroki Nakamura, Hiroshi Sakuraba, Fujio Masuoka
"Analysis of
the subthreshold characteristics for the FC-SGT flash memory cell,"
Electronics
and Communications in Japan (Part II: Electronics), Vol. 89, Issue 8, August
2006, pp. 34-41.
J. Yu, K. Aflatooni,
"Leakage current in DRAM memory cell",
2006 16th Biennial University / Goverment / Industry Microelectronics Symposium, 2007, pp. 191-194.
Kuk-Hwan KIM, Hyunjin LEE, and Yang-Kyu CHOI,
"Novel
Structures for a 2-Bit per Cell of Nonvolatile Memory Using an Asymmetric
Double Gate"
IEICE Transaction on Electronics, Vol. E89-C, NO.5 MAY 2006
