Silvaco IP Symposium

IoT, Automotive, Mobile SoC Success with SIPware from Silvaco.

Fun Prizes Join us at this year’s Silvaco's China IP Symposium in Shanghai. This event will introduce the latest Silvaco SIPware design IP and Xena IP management technology. Symposium topics include design challenges and IP solutions for a wide variety of applications and markets in AI, automotive, IoT, and cloud computing. Designers will also learn how address evolving power/performance/area (PPA) needs and process node developments, with custom-tailored digital cell libraries.

研讨会时间及地点:

  • 星期二, 2019/3/26
  • 上海搏雅酒店
  • 上海市浦东新区张江高科技园区碧波路699号



会议结束时有机会赢取时尚酷炫大奖 !

Giveaways


会议议程

Time
12:00 - 13:00 自助午餐及现场注册
13:00 - 13:05 欢迎致辞 - Sharon Fang General Manager, Silvaco China
13:05 - 13:40 半导体市场趋势,市场及Silvaco
Jai Durgam Vice President, General Manager, IP Business Unit
The AI/ML, IoT and Automotive market segments have propelled the growing need for standards-based semiconductor design IP. In this presentation we will discuss the market trends, requirements of these markets and an give an overview of how Silvaco SIPWare is addressing these demands.
13:40 - 14:20 用于IoT及车载的接口IP核及IP子系统
Rajeev Huralikoppi Field Applications Engineer, IP Business Unit
The explosive growth in the deployment of sensors and cameras in IoT, Automotive and Industrial applications require high speed, low-power interfaces and subsystems that are available in a tight time-to-market window. See how Silvaco’s comprehensive SIPWare suite helps semiconductor companies meet these requirements.
14:20 - 14:50 多种车载通讯协议及IP解决方案
Thomas Blaesi Vice President, Global Marketing
The Automotive market uses a suite of standards-based IP for the various electronics throughout the vehicle, from simple cabin-comfort controls, to complex drive-train management, and to ADAS applications. In this presentation, Thomas Blaesi will discuss the relevant standards and protocols, and how Silvaco SIPWare is a complete provider of these solutions.
14:50 - 15:15 茶歇
15:15 - 15:45 独特的Xena IP管理软件系统
Jai Durgam Vice President, General Manager, IP Business Unit
Now that design IP is reused in over 50% of new SoCs, it is critical that semiconductor companies have a methodology and the infrastructure to manage the multiple sources, licenses and control of design access. Silvaco Xena IP Management Platform is the ideal solution for enterprises, that scales from start-ups to very large semiconductor and system companies. Xena's capabilities and features will be shown to effectively manage your company-wide internal and third-party IP portfolio.
15:45 - 16:25 利用Silvaco基础IP构建优化的标准单元库
Jens Michelsen Director Business Development
To address evolving power/performance/area (PPA) needs and process node developments, designers of digital CMOS ICs need to custom-tailor digital cell libraries and explore the impact of alternate device models, design rules and cell architectures, as well as process migration. Silvaco Cello will be presented, including how to easily control and alter the individual attributes of all digital library cells, making precise adjustments to cell parameters to fulfill the strictest design requirements.
16:25 幸运大抽奖

*Sessions and times are subject to change without notice.

Symposium Highlights:

Sharon Fang
欢迎致辞 Sharon Fang
General Manager, Silvaco China

Sharon Fang is a seasoned executive with a distinctive combination of sales, marketing, strategic thinking and operational skills, successful track record and driving revenue growth as both an individual contributor and sales manager in EDA. Sharon currently serves as General Manager for Silvaco China. In her role as head of China region, Sharon is putting together the necessary processes and infrastructure to streamline the sales process, empowering individuals and teams to maximize value to customer as well as ROI. The China organization is focused on helping drive customer success through the use of Silvaco TCAD-to-sign off solutions, modeling services, IP management & compliance software while driving business growth for the company.

Jai Durgam
半导体市场趋势,市场及 Jai Durgam
Vice President, General Manager, IP Business Unit
Jai Durgam brings nearly 30 years of experience in the design, IP and EDA space. Most recently, Jai was the Vice President for Customer Design Enablement at Globalfoundries where he led all enablement, from PDKs & models to IP and design solutions for all GF nodes, including 22FDX and 14nm. Prior to that, Jai spent 11 years at Synopsys in multiple roles. From 2011-2016, he led world-wide Field Applications for Synopsys’ Solutions group for five years, supporting the complete IP portfolio from Synopsys. Jai was Sr. Director of Applications Consulting and Design Services for Synopsys India. Jai started his career at National Semiconductor Corp and has worked at Silicon Image and Scintera Networks. Jai has a Masters in Computer Engineering and Science from Oregon State University.


Rajeev Huralikoppi
用于IoT及车载的接口IP核及IP子系统 Rajeev Huralikoppi
Field Applications Engineer, IP Business Unit

Rajeev Huralikoppi is Application Engineer in Silvaco’s IP Division. He is responsible supporting the products of the I3C family. He brings over 25 years of experience in the Silicon Valley working for various companies like Synopsys, IPExtreme, Virtual Power Systems in the field of using IPs in ASIC and FPGA design. Rajeev Huralikoppi holds an MSEE in Electrical Engineering from University of Alabama in Huntsville in 1990.


Thomas Blaesi
多种车载通讯协议及IP解决方案 Thomas Blaesi
Vice President, Global Marketing
Thomas F. Blaesi is Vice President of the global marketing group, which is chartered with defining, driving, and promoting Silvaco’s leadership in the TCAD, EDA and IP market. Key areas of responsibility include strategic planning, corporate marketing, product marketing, market research, brand management, corporate communications, and ecosystem alliance programs.

Thomas joined Silvaco in October 2017 with more than 25 years of experience in corporate strategy, business development, and marketing in semiconductor, and electronic design automation industries. He has led major projects in SoC platform-based design, system-level design, and design for manufacturing in addition to hands-on experience in custom and semi-custom chip design and development.

Most recently, Thomas was the managing partner at Zeema Technologies. Before that, he served as CEO of Chipvision, and held various senior business and technical positions at Cadence, Synopsys, and LSI Logic.

Thomas holds a BS in electrical engineering and computer science from Hochschule Furtwangen University, Germany.

Jai Durgam
独特的Xena IP管理软件系统 Jai Durgam
Vice President, General Manager, IP Business Unit
Jai Durgam brings nearly 30 years of experience in the design, IP and EDA space. Most recently, Jai was the Vice President for Customer Design Enablement at Globalfoundries where he led all enablement, from PDKs & models to IP and design solutions for all GF nodes, including 22FDX and 14nm. Prior to that, Jai spent 11 years at Synopsys in multiple roles. From 2011-2016, he led world-wide Field Applications for Synopsys’ Solutions group for five years, supporting the complete IP portfolio from Synopsys. Jai was Sr. Director of Applications Consulting and Design Services for Synopsys India. Jai started his career at National Semiconductor Corp and has worked at Silicon Image and Scintera Networks. Jai has a Masters in Computer Engineering and Science from Oregon State University.

Jens C. Michelsen
利用Silvaco基础IP构建优化的标准单元库 Jens C. Michelsen
Director of Business Development
Mr. Michelsen was Director of Physical Design at Vitesse’s Ethernet Products Division. Before joining Vitesse, he served as Physical Design Manager of Exbit Technology. Mr. Michelsen has more than 15 years’ industry experience within leading companies including Intel, Olicom and GN Nettest, in areas ranging from mathematical modeling to physical design. In recent years, physical design and design flow to tapeout have been his main focus. He holds several US patents in communications and IC design.