Managing Design Technology Co-Optimization (DTCO) Using One Command File

This webinar illustrates the advantages of using a single command file and a GDSII layout to create an entire Design Technology Co-Optimization (DTCO) experiment set, using physics-based 3D active devices and Back End Of Line (BEOL) interconnect cell level structures, for extraction of the active device Spice model parameters and extracted RC parasitics using a 3D field solver, and for final Spice circuit simulation. A FinFET based technology will used as a working example, but other technology types can be used with equal effect.

What attendees will learn:

How this enabling technique facilitates communication between engineers from different departments in circuit design, since all departments can directly observe the effects of their changes on the final circuit performance, even if individual engineers contributing to various sections of the flow have limited knowledge of the tool syntax in the other flow sections.

For example, a process engineer can experiment with different process flows, modifying only the process simulation section, and without any required knowledge of device physics, back-end design or Spice circuit syntax, can re-run the single input command file, and see the effect of his or her design changes on the final circuit performance, including interconnect parasitic effects.

All the sections and necessary stages of the DTCO command flow will be presented in detail.


Presenter:

Derek Kimpton Dr. Derek Kimpton is the Principal Applications Engineer for Silvaco's TCAD division and has been a part of the Applications team at Silvaco's head office in Silicon Valley continuously for over 21 years.

Prior to that, he researched the feasibility of SiGe layer synthesis using germanium implantation and worked in the characterization of radiation-tolerant Silicon on Sapphire and other SOI technologies. His PhD work at King's College, London involved the full process development and electrical characterization of gallium indium arsenide transistors including material analysis, fabrication equipment design and the creation of test mask sets.


Who should attend:

Engineers, management and academics looking for layout, process, device, BEOL, MEOL or circuit design solutions for co-optimization of the entire device design flow, using physics-based simulations.